A typical system having an embedded Time of day feature (eTod) is shown in FIG. 1. A transmitter 10 has two clock reference inputs (signal ref1 at reference numeral 12 and signal ref2 at reference numeral 14).
In the following description, the clock reference signal ref1 is specified as a normal local reference clock and the clock reference signal ref2 provides updated time of day information in the form of a clock signal, for example a 1 Hz clock signal, synchronized to a time standard such as Coordinated Universal Time. The clock output at out1 at reference numeral 40 is locked to the clock reference signal ref1. The clock output at out2 at reference numeral 52 in FIG. 1 is the clock which is locked to the time of the day.
The clock reference signal ref1 presented at reference numeral 12 and the clock reference signal ref2 presented at reference numeral 14 are both 50% duty cycle square waves. The frequencies of the clock reference signals ref1 and ref2 need not be related to each other. The clock reference signal ref1 presented at the clock reference input ref1 12 is provided to phase acquisition unit (PA) 16 where its clock phase with respect to the phase of a local clock internal to the transmitter 10 is extracted. The clock reference signal ref2 presented at the clock reference input ref2 14 is provided to phase acquisition unit (PA) 18 where its clock phase with respect to the phase of the local clock internal to the transmitter 10 is extracted.
A digital phase locked loop (DPPL0) 20 is phase locked to the ref1 clock reference signal ref1. Its output is presented to clock synthesizer 22, whose output is therefore phase locked to the clock reference signal ref1. The phase difference between the output of the DPLL0 20 and the clock reference signal ref2 at the output of the phase acquisition unit 18 is determined in a subtractor circuit 24 and is encoded in encoder 26. The encoded phase difference at the output of encoder 26 is used by modulator 28 to modulate the output of the clock synthesizer 22 by changing the duty cycle of the output of the clock synthesizer 22 from the DPLL0 20 to generate a ref(encoded) signal at its output. As an example, a 25% duty cycle can be used to represent a “zero” bit and a 75% duty cycle can be used to represent a “one” digital bit. The ref(encoded) signal at the output of modulator 28 is also phase locked to the clock reference signal ref1.
A receiver 30, may be located at a random distance from the transmitter 10. On the receiver end, the receiver 30 receives the ref(encoded) reference signal from the output of the modulator 28 in the transmitter 10 on input 32. The ref(encoded) reference signal is presented to phase acquisition unit (PA) 34 where its clock phase with respect to the phase of a local clock 36 internal to the receiver 30 is extracted. A first digital phase locked loop (DPPL1) 38 is coupled to the phase acquisition unit 34. Its output is presented to clock synthesizer 40, that generates the output signal out1 at reference numeral 42 that is phase locked to the received ref(encoded) clock reference input signal.
The phase difference information between clock reference signals ref1 and ref2 that was encoded in the ref(encoded) signal is demodulated by demodulator 44 and decoded in phase decoder 46. The phase difference information is then subtracted from the phase of the ref(encoded) reference signal (which has the same phase as the ref1 reference signal) in subtractor circuit 48 to obtain a (delayed) phase of clock reference signal ref2 that is presented to a second digital phase locked loop DPLL2 50. The output of DPLL2 50 is presented to clock synthesizer 52, that generates the output signal out2 at reference numeral 54 which is locked to the clock reference signal ref2. The combination of DPLL2 50 and clock synthesizer 52 thus represents an embodiment of a circuit for generating the recovered second signal. The phase locking circuits, i.e., the first digital phase locked loop (DPPL1) 38 and the second digital phase locked loop (DPLL2) 50 are being described herein as digital phase locked loops, it being understood that this is a particular non-limiting embodiment of a phase-locked loop circuit.
In actual applications, such as in the embedded Time of day (eTod) application, where clock reference signal ref1 is the clock to be used for synchronization output (out1) 42 and clock reference signal ref2 contains the information for time of the day which is output at line out2 54, some time is required to transmit the encoded data from the transmitter 10 to the receiver 30. In the present invention, the time T that it takes to transmit all of the bits contained in a digital number that defines the phase difference between the clock reference signals ref1 and ref2 will be referred to herein as a decode frame. In the transmitter 10, the phase difference is calculated at the time when a decode frame starts at the output of the clock synthesizer 22. Depending on the number of bits needed to specify the phase difference between the clock reference signals ref1 and ref2, the digital number representing the phase difference between the clock reference signals ref1 and ref2 signals can require many clock cycles to be completely transmitted. In the receiver 30, the phase decoder 46 starts at the decode frame starting time and the phase difference can be completely demodulated at a delay time that is Td seconds later than the decode frame starting time, where Td is the time delay it takes to completely demodulate and decode the phase difference information. This time delay Td is longer if the carrier clock frequency is low and the required number of bits for encoding the phase difference between the clock reference signals ref1 and ref2 is larger to provide better resolution of the phase difference. This time delay Td will increase the lock time for the second digital phase locked loop DPLL2 50 and if it is too long may cause the second DPLL2 50 to become unstable.
The receiver 30 of FIG. 1 is used where a direct encoding method is assumed for the encoder/decoder of the phase difference between the clock reference signals ref1 and ref2. Where a direct encoding method is used, the output from the phase decoder 46 of FIG. 1 is used to obtain the clock reference signal ref2 signal phase by subtracting the output of the phase decoder 46 from the output of phase acquisition unit 34 in subtractor circuit 48.
In most cases phase decoder 46 is required because an indirect encoding method, such as delta-modulation encoding, is likely to be used for more efficient data transmission, because it requires fewer bits to be transmitted than the number of bits that are required using direct encoding. The function of demodulator 44 is to extract the bits representing the encoded phase difference and present the demodulated phase difference data to the phase decoder 46. The phase decoder 46 takes the demodulated bits from the demodulator 44 and from them generates a number that is the phase difference between the ref1 and ref2 signals. The detailed functioning of the phase decoder 46 depends on the modulation method used by the encoder 26 of FIG. 1 and persons of ordinary skill in the art will easily be able to configure the phase decoder 46 for any given modulation method.
As previously mentioned, the decoded phase adjustment represents the phase difference between the clock reference signals ref1 and ref2 at the decode frame starting time in the transmitter and there is a delay of Td seconds needed to completely decode the phase difference information at the receiver after arrival of the beginning of the decode frame. In addition, the output of the PA 34 represents reference phase value at the sample time with respect to a local clock in the receiver 30 which is not aligned with the input clock cycle (hence the decode frame boundary). All these factors will cause noise at the phase input to the second DPLL2 50 that will cause the second DPLL2 50 to take a long time to be phase locked. In some cases, the second DPLL2 50 may become unstable if the clock rate is slow and results in a long decode frame period. The worst-case time delay Td could be one decode frame cycle. This is because all data representing the phase difference between the clock reference signals ref1 and ref 2 may require an entire decode frame cycle to be transmitted.